1. Field of the Invention
The present invention relates to semiconductor devices and methods of fabricating the same.
2. Description of the Related Art
Mask ROMs are largely divided into NAND-type ROMs and NOR-type ROMs. While the NAND-type ROM has a slow operating speed, it is adequate for high integration due to its small unit cell area. On the other hand, the NOR-type ROM has a high operating speed, but is not suitable for high integration due to its great unit cell area. Therefore, a flat NOR-type ROM structure, which enables both a high operating speed of the NOR-type ROM and a small cell area of the NAND-type ROM, has been proposed. The flat NOR-type ROM is a type of mask ROMs in which a device isolation layer and a contact plug are not included in a unit cell. The flat NOR-type ROM adopts a buried impurity region disposed in a semiconductor substrate as a bit line.
FIGS. 1 to 3 are cross-sectional views illustrating a method for fabricating a conventional flat NOR-type ROM semiconductor device.
Referring to FIG. 1, a buffer oxide layer 20, an anti-reflecting layer 30, and a photoresist layer are sequentially formed on a semiconductor substrate 10. The photoresist layer is patterned using a typical photolithographic process, thereby forming a photoresist pattern 40 that exposes a region of the anti-reflecting layer 30. The anti-reflecting layer 30 is used to form the photoresist pattern 40 and is typically composed of silicon oxynitride (SiON).
Next, an ion implantation process is implemented using the photoresist pattern 40, as an ion implantation mask, to form an impurity region 50 in the semiconductor substrate 10. Through the ion implantation process, arsenic (As) ions are implanted into the semiconductor substrate 10, penetrating the anti-reflecting layer 30 and the buffer oxide layer 20. At this time, silicon atoms of the semiconductor substrate 10 are deviated from a lattice structure by a kinetic energy of the arsenic ions. As a result, the impurity region 50 has lattice defects.
Referring to FIG. 2, after forming the impurity region 50, the photoresist pattern 40 is removed to expose the anti-reflecting layer 30. Thereafter, the exposed anti-reflecting layer 30 is removed using an etchant containing phosphoric acid (H2PO4).
Etching of the anti-reflecting layer 30 using the phosphoric acid may cause etching damages to the buffer oxide layer 20 thereunder. That is, the buffer oxide layer 20 may suffer from an increase in thickness deviation as well as degradation of physical/electrical (device) characteristics. Thus, the buffer oxide layer 20 is not used for a gate insulation layer of a transistor and is thus removed by an etchant containing a fluoric acid. As a result, as illustrated in FIG. 2, the entire top surface of the semiconductor substrate 10 is exposed.
Referring to FIG. 3, a gate insulation layer 60 and 65 is formed on the semiconductor substrate 10, in which the buffer oxide layer 20 is removed. The process of forming the gate insulation layer 60 and 65 is an important process determining characteristics of MOS transistors. The gate insulation layer 60 and 65 is typically formed by thermally oxidizing the exposed semiconductor substrate 10.
The thermal oxidization process is typically conducted at approximately 850° C. Such a high-temperature thermal oxidization may, however, cause diffusion of impurities in the impurity region 50. Thus, the impurities in the impurity region 50 can be diffused to form a buried impurity region 55 having a greater width and depth. The buried impurity regions 55 serve as source/drain regions of the flat NOR-type ROM and as interconnections for connecting the source/drain regions.
The gate insulation layer 60 and 65 should be formed to a predetermined thickness (tox) or more to fabricate a reliable MOS transistor. However, as illustrated in FIG. 2, the top surface of the semiconductor substrate 10 is completely exposed during removal of the anti-reflecting layer 30. Thus, while the gate insulation layer 60 is formed to the thickness of the impurities As in the impurity region 50 can be excessively diffused. As a result, the distance 11 between the adjacent buried impurity regions 55 is reduced, causing a short channel effect, impeding high integration of semiconductor devices.
Further, in the thermal oxidization, the impurity region 50 having lattice defects is easily and rapidly oxidized as compared with other regions on the semiconductor substrate. Thus, the gate insulation layer 65 formed on the impurity region 50 has a thickness greater than that formed on the other regions, which also is not desirable for high integration of semiconductor devices.